movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r22=[r22];;
adds r22=IA64_VCPU_META_SAVED_RR0_OFFSET,r22;;
- ld4 r23=[r22];;
+ ld8 r23=[r22];;
mov rr[r0]=r23;;
srlz.i;;
st4 [r20]=r0 ;;
movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r22=[r22];;
adds r22=IA64_VCPU_META_RR0_OFFSET,r22;;
- ld4 r23=[r22];;
+ ld8 r23=[r22];;
mov rr[r0]=r23;;
srlz.i;;
adds r21=1,r0 ;;
dep r23=r28,r23,16,8;;
dep r23=r29,r23,8,8
cmp.eq p6,p0=r25,r0;; // if rr0, save for metaphysical
-(p6) st4 [r24]=r23
+(p6) st8 [r24]=r23
mov rr[r8]=r23;;
// done, mosey on back
1: mov r24=cr.ipsr
struct arch_domain {
struct mm_struct *active_mm;
struct mm_struct *mm;
- int metaphysical_rr0;
- int metaphysical_rr4;
+ unsigned long metaphysical_rr0;
+ unsigned long metaphysical_rr4;
int starting_rid; /* first RID assigned to domain */
int ending_rid; /* one beyond highest RID assigned to domain */
int rid_bits; /* number of virtual rid bits (default: 18) */
unsigned long xen_timer_interval;
#endif
mapped_regs_t *privregs; /* save the state of vcpu */
- int metaphysical_rr0; // from arch_domain (so is pinned)
- int metaphysical_rr4; // from arch_domain (so is pinned)
- int metaphysical_saved_rr0; // from arch_domain (so is pinned)
- int metaphysical_saved_rr4; // from arch_domain (so is pinned)
+ unsigned long metaphysical_rr0; // from arch_domain (so is pinned)
+ unsigned long metaphysical_rr4; // from arch_domain (so is pinned)
+ unsigned long metaphysical_saved_rr0; // from arch_domain (so is pinned)
+ unsigned long metaphysical_saved_rr4; // from arch_domain (so is pinned)
int breakimm; // from arch_domain (so is pinned)
int starting_rid; /* first RID assigned to domain */
int ending_rid; /* one beyond highest RID assigned to domain */